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ECSE 530 Logic Synthesis (3 unit茅s)

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Nota : Ceci est la version 2017鈥�2018 de l'annuaire 茅lectronique. Veuillez mettre 脿 jour l'ann茅e dans la barre d'adresse de votre navigateur pour une version plus r茅cente de cette page, ou .

Offered by: G茅nie 茅lectr. et informatique (G茅nie et l'architecture)

Vue d'ensemble

G茅nie 茅lectrique : The place of logic synthesis in microelectronics. Representations of Boolean functions: logic covers, binary decision diagrams. Two-level synthesis algorithms, Espresso. Multi-level synthesis to Boolean networks: don't care methods, algebraic optimizations, delay modelling. Sequential synthesis: state-based optimizations, state assignment, network optimizations. Technology mapping: library cell and FPGA mapping.

Terms: This course is not scheduled for the 2017-2018 academic year.

Instructors: There are no professors associated with this course for the 2017-2018 academic year.

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